1. Field of the Invention
This invention relates to a thermoplastic semiconductor package and to a method of making it, and more particularly concerns attaching a thermoplastic lid or cover to a thermoplastic cavity type semiconductor package body by ultrasonic welding. The semiconductor package may be a Plastic Quad Flat Pack package (PQFP) as shown in FIGS. 1 and 11, Plastic Dual In-Line Package (PDIP) as shown in FIGS. 3 and 13, or a Plastic Pin Grid Array package (PPGA) as shown in FIG. 4, and may include Small Outline Integrated Circuit (SOIC) variations, but is not limited thereto. The semiconductor package may include single or multiple Integrated Circuit (IC) arrangements.
The term "Plastic Cavity Type Semiconductor Package" refers to any type of semiconductor package that provides for the mounting of an integrated circuit die onto the die pad of the semiconductor package through a recess or cavity in the semiconductor package, subsequently adding electrical interconnections and sealing the electrical components by applying a sealant over the wires and die.
The terms "lid" or "cover" as used in this disclosure are interchangeable, and refer to any component that is attached to the main body of a semiconductor package to protect the internal components of the semiconductor package, such as the integrated circuit, from environmental or physical damage or contamination. The design of the lid may be such to fit within the constraints of a cavity in the semiconductor package body. Alternatively, if desired, the lid may be an integral component of the overall cover of the device. The term lid does not define top or bottom.
The term "ultrasonic welding" refers to a method of welding elements together by producing an intense, controlled vibration from an ultrasonic welding booster horn and applying it to the elements to be welded. This intense controlled vibration, coupled with an application of a set pressure against the components to be welded, develops frictional heat which causes melting of one or both of the components at the interface between the components, and creates a mechanical bond between the components.
A plastic cavity type semiconductor package is a practical vehicle for the mounting of a sub-miniature integrated circuit to printed circuit or wiring board. Plastic cavity-type semiconductor packages contain an integrated circuit which is electrically interconnected to an integral polyester, epoxy or polyimide resin base laminated substrate with an integral electrical circuit, or to an integral conductive lead frame. The substrate circuit or lead frame enlarges the effective pitch, or spacing, between electrical connections of the integrated circuit to a practical, useable dimension found on printed circuit or wiring boards. The method of enlargement may be by a flexible or rigid substrate circuit, a stamped or chemically etched conductive lead frame, or a combination of a substrate circuit and a conductive lead frame.
The ways of mounting a plastic cavity type semiconductor package onto a printed circuit or wiring board varies from insertion or through hole mounting to surface mounting.
The particular way of mounting dictates the arrangement of the electrical leads that interface with the printed circuit or wiring board.
The method of pitch enlargement typically utilized for Plastic Quad Flat Pack (PQFP) and Plastic Dual In-Line Packages (PDIP) may be either an integral substrate circuit electrically connected to the internal ends of a lead frame, whereby the external ends of the lead frame interface the printed circuit or wiring board, or an integral lead frame whereby the integrated circuit is electrically connected to the internal ends of the lead frame and the external ends interfacing the printed circuit or wiring board. The interface may be a surface mount or insertion type interface.
The method of enlargement typically utilized for a Plastic Pin Grid Array, (PPGA) may be an integral substrate circuit electrically connected to the internal ends of a conductive pin, whereby the pins form a matrix pattern and provide electrical connection to the printed circuit or wiring board by inserting the external ends of the conductive pin matrix into the printed circuit or wiring board.
Upon mounting the integrated circuit or die onto the die pad, a series of wire interconnections, or wire bonds, are made between the integrated circuit and the internal leads of a lead frame, or to a substrate circuit. In applications requiring sealed integrated circuits, a sealant is applied on and about the integrated circuit and the wire bond interconnections.
Plastic cavity type semiconductor packages are offered in various formats. Plastic Pin Grid Arrays, PPGA, for example, are available in a bare substrate circuit and pin matrix in which all the components compromising the semiconductor package are visible. A cavity, or recess, is designed into the substrate circuit for mounting of an integrated circuit die.
The PPGA is also available with the substrate circuit, and the interface of the pin matrix and the substrate circuit, pre-molded or encapsulated with a plastic molding compound. A cavity is designed into this package body for mounting an integrated circuit die and for electrically interconnecting the die to the substrate circuit.
The end user provides for the integrated circuit die mounting, the electrical interconnection of the integrated circuit to the substrate circuit and the protection of the integrated circuit by the application of a sealant or lid onto the semiconductor package.
In the case of a bare semiconductor package, a typical method of providing protection to the integrated circuit and electrical interconnection against environmental or physical damage involves the total encapsulation of the bare package with a molding compound, or the application of a "Blob Top", by placing a suitable quantity of sealant, in the cavity on top of the integrated circuit and electrical interconnections, and curing the sealant by applying heat or ultraviolet rays.
In the case of the pre-molded or encapsulated cavity package, a typical method of providing protection to the integrated circuit and electrical interconnection involves applying a "Blob Top" or attaching a lid over the cavity. In a typical lidding process, a suitable amount of adhesive is applied about the cavity opening or on the lid or, in some cases, both. The lid and package body are then mated together and allowed to cure by applying heat or ultraviolet rays. The actual application of the adhesive may be by dispensing a liquid material, screen printing a paste material, or applying a preformed adhesive material blank onto the components to be mated.
The disadvantages of the current methods of protecting the integrated circuit in a Plastic Cavity-Type Semiconductor Package include the following:
a. Adhesive bonding of the lid to the semiconductor package is a time consuming process that involves subjecting the assembly to possible contamination by the adhesive bonding agents.
b. Adhesive bonding agents, and sealing agents, curable by any method, are hydroscopic compounds which absorb moisture, and this moisture is introduced into the cavity and onto the electrical components, causing corrosion and failure.
c. Moisture within a lidded plastic cavity semiconductor package causes an increase in pressure within the cavity when subjected to elevated temperatures, such as soldering. The increase in pressure, due to the expansion of the moisture, raises internal pressures to a level which may cause the lid to separate from the assembly.
d. Encapsulation, or Blob Topping, is a time consuming process which involves subjecting the assembly to possible contamination by the sealing agent, possible failure of the assembly due to moisture introduction, and possible failure of the assembly due to thermal induced stress, and may cause separation or disconnection of the wire bond from the integrated circuit, or separation of the electrical interconnection to the semiconductor package. Heat curing of the sealant also causes thermal induced stress.
e. Over molding semiconductor packages with a plastic mold compound involves subjecting the assembly to possible wire sweeping, which occurs during the injection of the plastic molding compound. Wire sweeping may cause shorting between adjacent wire bonds, or may cause separation or disconnection of the wire bonds from the integrated circuit, or the electrical interconnection to the semiconductor package.
f. Stress critical integrated circuits may not be subjected to multiple cycles of elevated temperature, as the integrated circuit may crack o disconnect from the die mount surface. Failures due to stress cracking are increased by thermal cycling. An example of multiple thermal cycling: Die attaching requires the introduction of heat to cure the bonding agent, and Blob Topping requires heat to cure the sealant, and over molding, which is performed at elevated temperatures.
g. Additional handling of a semiconductor package during the process of adhesive bonding or sealing involves subjecting the assembly to possible contamination or physical damage which may cause failure.
h. A major disadvantage in the assembly of an over-molded or blob topped semiconductor package is noticed during thermal cycling. The differences in the coefficients of thermal expansion, the rate in which a material expands or contracts in response to temperature changes, of the integral components, i.e., the die, the die attach agents, the wire interconnections, the encapsulation material, and so on, are such that when the assembly is subjected to thermal cycling, multiple exposures to hot and cold temperatures, the components expand or contract at different rates. Thermal cycling causes stress and/or strain upon the components due to the differences in those rates and may cause component failure due to wear out, disassociation of surfaces, or fractures of the integral components. Also, the larger dies which are now utilized, include integral fine line geometry. During thermal cycling, the differences in thermal expansion may cause the fine line geometry to crack or separate due to the stresses upon the die surface caused by the expansion of the encapsulation material against the die surface. This is an increasing occurrence due to the increased use of large, fine line geometry, stress critical dies. Another disadvantage of thermal cycling and the problem associated with thermal expansion, is the additional potential for failure due to corrosion or lid separation. As the integral components expand and/or contract during thermal cycling, pockets or voids are created. These pockets or voids allow moisture to gather. Moisture within a semiconductor package causes failures due to corrosion or increase in internal package pressure.